Verilog HDL – How to store data from a file to an array of registers
Following test bench shows you how to store data from a file to an array of registers. This, will be useful in if you are making an instruction memory or data memory sort of module.
Here, we will read the “data.txt” file which will contain 32 bit number lines separated by new lines like shown below.
data.txt file
00010000000000000000000011111111 10000100000110100000000000000000 00010000000000000000000001010110 10000100000110110000000000000000 00010000000000000000000011111111 10000100000111000000000000000000 00010000000000000000000001010110 10000100000111010000000000000000 00010000000000000000000011111111 10000100000111100000000000000000
Here is the “test.v” verilog file, which will contain our test bench stimulus module
test.v file
module stimulus; parameter SIZE=10; parameter DATA="data.txt"; //data file name here reg [31:0] memory [0:SIZE-1]; //create array of 32bit sized array integer i; initial begin $readmemb(DATA,memory); //loading data(bit) into memory //$readmemh(INSTRUCTION_DATA,memory); //loading data(hex) into memory for(i=0;i<SIZE;i=i+1) begin $display("memory[%0d] = %b",i,memory[i]); end end endmodule
Here is the cmd output